The present invention relates to semiconductor processing and particularly to processing of silicon germanium (SiGe) bipolar junction transistorxe2x80x94complementary metal oxide semiconductor (BiCMOS) technology.
The combination of bipolar junction transistor (BJT) and field effect transistor (FET) devices on the same semiconductor substrate can pose processing problems since different processes are required to form each type of transistor. A BJT typically consists of a base/emitter/collector structure formed by the deposition and etching of layers of different materials. Typically, the base, emitter and collector of the BJT are electrically isolated from each other by at least one layer of dielectric material. An FET typically consists of a source/drain/gate structure where the source and drain are doped regions within the semiconductor substrate and the gate is formed on top of the semiconductor substrate between the source and drain regions. The gate is typically made of at least one layer of material and forms a raised region on the substrate.
During processing to form the FETs, high temperatures may be required for processes such as annealing or film deposition. For BiCMOS technologies where the high temperatures used to form the FETs exceed the thermal budget of the BJTs, the BJTs are formed after the FETs. With the gate structure of the FETs formed as raised regions on the substrate and the BJTs formed by the deposition and etching of layers of different materials, process problems are encountered.
The current invention will describe a method to utilize a sacrificial film to eliminate the problem of residual thin films remaining between the gates of FETs during the formation of the BJTs in a BiCMOS device. The BiCMOS device is formed on a semiconductor substrate. The method of the current invention includes processing the substrate to form the FETs of the BiCMOS device. The FET consists of a source/drain region, gate oxide, gate films and gate spacer oxide resulting in raised and recessed regions on the surface of the semiconductor substrate. A thin FET protection layer is then deposited on the surface of the semiconductor substrate. A selectively removable filler layer is then deposited on the FET protection layer and over-fills the recessed regions. The selectively removable filler layer is planarized down to the top of the raised regions and thus substantially fills the recessed regions. An opening is made in the selectively removable filler layer in the region where the BJT is to be formed. Multiple layers of different materials are deposited and removed during the construction of the BJT. Since the recessed regions of the FETs are filled with the selectively removable filler layer, little to none of the layers of different materials are deposited in the recessed regions allowing for easy removal of the layers. After removal of the multiple layers of different materials from the FET region, the selectively removable filler layer and the FET protection layer are also removed resulting in recessed regions between the gates of the FETs free from residual thin films.
The advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.